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W631GG6KB
8.3.2
Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength,
Rtt_Nom impedance, additive latency, Write leveling enable and Qoff. The Mode Register 1 is written
by asserting low on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling
the states of address pins according to the Figure 6 below.
BA2
0 * 1
BA1
0
BA0
1
A12
Qoff
A11
0 * 1
A10
0 * 1
A9
Rtt_Nom
A8
0 * 1
A7
Level
A6
Rtt_Nom
A5
D.I.C
A4
WR AL
A3
BT
A2
Rtt_Nom
A1
D.I.C
A0
DLL
Address Field
Mode Register 1
BA1
0
0
1
BA0
0
1
0
MR Select
MR0
MR1
MR2
A9
0
0
0
A6
0
0
1
A2
0
1
0
Rtt_Nom *3
Rtt_Nom disabled
RZQ/4
RZQ/2
A0
0
1
DLL Enable
Enable
Disable
1
1
MR3
0
1
1
RZQ/6
A5
A1
Output Driver
Impedance Control
Write leveling enable
1
0
0
RZQ/12* 4
0
0
RZQ/6
A7
0
1
Write leveling enable
Disabled
Enabled
1
1
1
0
1
1
1
0
1
RZQ/8* 4
Reserved
Reserved
0
1
1
1
0
1
RZQ/7
Reserved
Reserved
Note: RZQ = 240 ohms
Note: RZQ = 240 ohms
A12
Qoff *2
0
1
Output buffer enabled
Output buffer disabled *2
A4
0
0
1
1
A3
0
1
0
1
Additive Latency
0 (AL disabled)
CL-1
CL-2
Reserved
Notes:
1. BA2, A8, A10 and A11 are reserved for future use and must be programmed to 0 during MRS.
2. Outputs disabled - DQs, DQSs, DQS#s.
3. In Write leveling Mode (MR1 A[7] = 1) with MR1 A[12]=1, all Rtt_Nom settings are allowed; in Write Leveling Mode (MR1 A[7]
= 1) with MR1 A[12]=0, only Rtt_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
4. If Rtt_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
Figure 6 – MR1 Definition
8.3.2.1
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization,
and upon returning to normal operation after having the DLL disabled. During normal operation (DLL-on)
with MR1 (A0 = 0), the DLL is automatically disabled when entering Self Refresh operation and is
automatically re-enabled upon exit of Self Refresh operation. Any time the DLL is enabled and
subsequently reset, t DLLK clock cycles must occur before a Read or synchronous ODT command can be
issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for
synchronization to occur may result in a violation of the t DQSCK , t AON or t AOF parameters. During t DLLK ,
CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any Write operation,
except when Rtt_WR is enabled and the DLL is required for proper ODT operation. For more detailed
information on DLL Disable operation refer to section 8.6 “ DLL-off Mode ” on page 25.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be
disabled by continuously registering the ODT pin low and/or by programming the Rtt_Nom bits
MR1{A9,A6,A2} to {0,0,0} via a mode register set command during DLL-off mode.
Publication Release Date: Dec. 09, 2013
Revision A05
- 20 -
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